The present invention relates generally to bipolar transistor output stages, such as comparator output stages and amplifier output stages, and more particularly to circuitry for preventing or reducing problems associated with saturation of transistors in the output stages.
A bipolar transistor has a characteristic reverse recovery time, which is the time required for a transistor in its saturation mode to re-enter its active mode of operation. The recovery time is a process-controlled parameter, and the circuit has to be designed to “work around” the recovery time of the saturated transistor because it slows the circuit response time. (When a bipolar transistor is driven into saturation, charge accumulation occurs in its base region. If the transistor has to quickly switch into its active mode, then a discharge path has to be provided at its base electrodes. Conventional methods used to achieve the discharge path limit the output voltage swing of the collector of the transistor to at least 1 VBE voltage above the negative supply voltage rail. However, in some applications it may be necessary for the collector to be able to swing closer to the negative supply voltage rail.
FIG. 1 shows a known comparator 1-1 including a conventional differential input stage 10 having a (+) input coupled to receive a first input signal and a (−) input coupled to receive a second input Vin−. The output of input stage 10 is connected by conductor 11 to the input of an output stage 2-1. Output stage 2-1 includes a PNP input or follower transistor Q1 having its base connected to conductor 11. Output stage 2-1 also includes a clamping transistor Q6 having its emitter connected to conductor 11. The base of transistor Q1 is connected to conductor 11. Output stage 2-1 also includes a NPN follower transistor Q2 and a NPN output transistor Q3. The collector of transistor Q1 is connected to VSS, and the emitter of transistor Q1 is connected by conductor 13 to one terminal of a current source I1 and to the base of transistor Q2. The other terminal of current source I1 is connected to VCC, and a collector of transistor Q2 is also connected to VCC. The emitter of transistor Q2 is connected by conductor 15 to one terminal of a current source I2 and to the base of output transistor Q3, the emitter of which is coupled to VSS by a resistor R1. The other terminal of current source I2 is connected to VSS. The collector of output transistor Q3 is connected to comparator output conductor 18, on which a comparator output signal Vout is produced. The base of a clamping transistor Q6 is connected to conductor 15. The collector of clamping transistor Q6 is connected to output conductor 18, and the emitter of clamping transistor Q6 is connected by conductor 11 to the output of differential input circuit 10.
In the present example, output transistor Q3 is composed of 10 identical PNP parallel-connected “unit transistors”, each of which has its collector connected to output conductor 18 and its emitter connected to one terminal 16-1, 2 . . . 10 of a separate corresponding “unit” resistor R1-1, 2 . . . 10, respectively. The 10 unit transistors of which output transistor Q3 is composed are collectively referred to as “output transistor Q3” or are individually referred to as “unit transistors Q3-1, 2 . . . 10”. The other terminals of each of the 10 unit resistors R1-1, 2 . . . 10 are connected to VSS. The 10 unit resistors R1, 2 . . . 10 are collectively referred to as “resistor R1”. Output transistor Q3 can also be a single transistor capable of driving large load current.
In operation, input stage 10 of comparator 1-1 generates a voltage V11 on conductor 11 and applies it to the base of transistor Q1, causing it to either be in its active mode or its cut off mode of operation. Transistor Q1 drives the base of NPN transistor Q2, the emitter of which drives the base of output transistor Q3 and the base of clamping transistor Q6. Clamping transistor Q6 is turned ON so as to operate in its reverse active mode when the collector of output transistor Q3 goes more negative than its base. (A transistor is in its reverse active mode when its collector is actually functioning as an emitter and its emitter is actually functioning as a collector.) This enables output transistor Q3 to drive comparator output voltage Vout very close to its emitter voltage and hence to the lower supply voltage VSS. Note that if the emitter and collector terminals of clamping transistor Q6 are reversed, there could be a relatively large reverse bias across its base-emitter junction. As disclosed in the subsequently mentioned incorporated-by-reference co-pending patent application by the present inventors, that may lead to permanent damage of clamping transistor Q6 due to hot carrier injection. However, the collector-base junction of a bipolar NPN transistor can withstand the large reverse bias without damage.
Although bipolar transistor operation in reverse active mode is very poor for most purposes, it detects when the collector of output transistor Q3 goes more negative than its base and turns clamping transistor Q60N in its reverse active mode. When that happens, clamping transistor Q6 causes current to flow out of conductor 11, through clamping transistor Q6 in its reverse direction, and into the collector of output transistor Q3. This reduces the base currents of transistors Q1 and Q2 and therefore reduces the base current of output transistor Q3 and therefore limits how much further output transistor Q3 can be driven into saturation. When output transistor Q3 is saturated, all of the unit transistors Q3-1, 2 . . . 10 connected in parallel are individually saturated.
When output transistor Q3 is ON, the collector-base junction of clamping transistor Q6 is forward biased, and provides negative feedback via the base-collector junction of output transistor Q3. The collector of output transistor Q3 is clamped to one forward diode voltage drop below its base and therefore prevents transistor Q3 from going into deep saturation. (A bipolar transistor is in “deep” saturation when its collector-emitter voltage is about 100 millivolts or less and its base-collector junction is forward biased and the reverse recovery time of the transistor becomes unacceptable for a particular circuit.) When output transistor Q3 is turned OFF, the negative feedback from the comparator output voltage Vout is disabled
Thus, in order to prevent output transistor Q3 from entering a state of deep saturation (e.g., with VCE (collector-emitter voltage) of less than about 100 millivolts), clamping transistor Q6, when turned ON in its reverse active mode, operates to clamp output voltage Vout to a base-collector junction voltage drop below the voltage on conductor 15, which is approximately equal to one VBE voltage lower than the voltage V11 at the output of input stage 10. However, the response time of output voltage Vout of comparator 1-1 is too slow to meet certain desired comparator delay requirements.
One of the disadvantages of output stage 2-1 in Prior Art FIG. 1 is that since output transistor Q3 has an inherent collector resistance, the current through it may already have driven output transistor Q3 into very deep saturation, making it too late for clamping transistor Q6 to be turned ON in its reverse active mode to forward bias its base-collector junction and clamp the base-collector voltage of output transistor Q3 so as to prevent it from being driven into very deep saturation. Furthermore, when output transistor Q3 is in very deep saturation, that results in a very large effective emitter-base capacitance in output transistor Q3. That in turn necessitates a relatively large amount of discharge time for turning output transistor Q3 OFF, and that may unacceptably limit how fast comparator output voltage Vout can be switched.
To avoid the foregoing shortcomings of output stage 2-1 in Prior Art FIG. 1, most comparators use CMOS output stages, which have a faster reverse recovery time; unfortunately, CMOS output stages also have slower overall response during active modes of operation. If a bipolar output transistor is used, its collector voltage is clamped to a level no lower than about 0.7 volt above the lower supply voltage VSS to avoid this problem, but this reduces the output voltage range of the comparator 1-1. CMOS output stages usually are used, because of their zero-DC gate current, in order to achieve a large current gain.
It should be understood that it may be necessary to utilize many emitter follower stages in the output stage of a bipolar transistor amplifier in order to obtain a suitably large current gain. However, this leads to a decrease in the operating signal voltage range with each additional current gain stage. That is especially problematic if the emitter follower stages become saturated and higher base current is required.
To overcome the foregoing problem, various known current boosting techniques have been used, but the known techniques utilize positive feedback, which is problematic in some cases. For example, current gain boosting has been achieved by connecting an additional transistor partly in parallel with the main output transistor (such as Q3 in Prior Art FIG. 1) and connecting the collector of an additional transistor to the input of a current mirror input to provide positive feedback in the output stage under consideration. Under certain circumstances, the amount of positive feedback may be far too great, causing unacceptable circuit instability, excessive power consumption, and/or lock-up behavior.
A conventional output circuit stage known as the Baker clamp provides positive feedback and is used in some power amplifiers. Details of the Baker clamp circuit presently are available at the website http://home.mira.net/˜gnb/audio/bakerclamp.html.
Thus, there is an unmet need for an output stage, such as a comparator output stage or an amplifier output stage, which substantially avoids problems associated with saturation of bipolar output transistors therein.
There also is an unmet need for a comparator (or amplifier) bipolar transistor output stage that prevents the comparator output voltage (or amplifier output voltage) from going into extreme saturation but nevertheless allows it to swing very close to the lower supply voltage VSS.
There also is an unmet need for a circuit that keeps an output transistor of a comparator from going into extreme saturation and nevertheless allows the output voltage of the comparator to swing very close to the lower supply voltage of the comparator.
There also is an unmet need for an amplifier having a bipolar transistor output stage capable of delivering a large output load current without having to use too many emitter follower stages to obtain the required current gain, and without substantially reducing the operating voltage range of the circuit of the output stage.